Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to an integrated circuit including a circuit for generating or transmitting a signal that swings in a current mode logic (CML) region and a method for operating the same.
In integrated circuits, a signal swinging in a CML region (hereinafter, referred to as a CML signal) is widely used in an input/output (I/O) interface for a high frequency signal such as a clock signal.
The CML region refers to a potential level region having a range defined by a certain DC potential level, or a potential level region having a range defined by an average potential level determined by a certain criterion. The CML signal refers to a signal toggling at a predefined frequency between a maximum potential level (Vmax) of the CML region and a minimum potential level (Vmin) of the CML region with a reference potential level in the CML region as the center.
For example, although a level of a power supply voltage (VDD) and a level of a ground voltage (VSS) in a device for inputting/outputting a CML signal are respectively 1.5 V and 0 V, the CML region may be defined in a range from 1.5 V to 1.0 V. A reference potential level of the CML region is 1.25 V, and the CML signal is a signal toggling at a predefined frequency and having a swing width of 0.5 V with 1.25 V at the center.
As described above, the CML region is designed to have a relatively small size compared with a potential level region defined by a level of a power supply voltage (VDD) and a level of a ground voltage (VSS) in a device for inputting/outputting a CML signal. This is because the CML signal is generally a high frequency clock signal.
That is, the CML region is a region defined for transferring a clock signal stably even though the clock signal is a high frequency clock signal ranging from several GHz to several tens of GHz or more.
For reference, because it is general that the CML signal toggles with a small swing range at a high frequency as described above, a potential level of the CML signal may change or the phase of the CML signal may be distorted due to a transmission noise thereof. What is therefore used is a differential scheme that simultaneously transmits two divided signals with opposite phases when transmitting the CML signal.
In integrated circuits, a signal swinging in a CMOS region (hereinafter, referred to as a CMOS signal) is widely used in an I/O interface for a signal which is used to determine its logic level like data.
The CMOS region refers to a potential level region defined by a level of a power supply voltage (VDD) and a level of a ground voltage (VSS). The CMOS signal refers to a signal toggling at a predefined frequency between a level of a power supply voltage (VDD), which is a maximum potential level (Vmax) of the CMOS region, and a level of a ground voltage (VSS), which is a minimum potential level (Vmin) of the CMOS region, with a half potential level between the level of the power supply voltage (VDD) and the level of the ground voltage (VSS) as the center.
Therefore, as described above, in the case of the CML region, even though the level of the power supply voltage (VDD) and the level of the ground voltage (VSS) are respectively 1.5 V and 0 V, the potential levels of 1.5 V and 1.0 V are specified as the CML region, so that the swing width of the CML signal may be 0.5 V. However, in the case of the CMOS region, when the level of the power supply voltage (VDD) and the level of the ground voltage (VSS) are respectively 1.5 V and 0 V, the potential levels of 1.5 V and 0 V are determined as the CMOS region. Thus, the swing width of the CMOS signal is 1.5 V.
For this reason, the swing range of the CMOS signal is inevitably lager than the swing range of the CML signal. This means that the CMOS signal is suitable to be used as data whose logic level is determined depending on the potential level.
FIG. 1 is a circuit diagram illustrating a circuit for generating or transferring a CML signal in a conventional integrated circuit.
An operation of the circuit is described below with reference to FIG. 1.
Referring to FIG. 1, a positive input signal INPUT_SIG and a negative input signal INPUT_SIGb have opposite phases. Also, a CML bias voltage CML_BIAS maintains a potential level corresponding to a logic high level. Thus, a third NMOS transistor N3 is turned on to transfer a constant current from a common node COMN to a ground voltage (VSS) terminal.
In this state, when a potential level of the positive input signal INPUT_SIG increases and a first NMOS transistor N1 is turned on, a voltage level of the negative input signal INPUT_SIGb decreases and a second NMOS transistor N2 is turned off. Accordingly, a predetermined current I1 continuously flows from a negative output node OUT_NDb to the common node COMN, but a current I2 does not flow from a positive output node OUT_ND to the common node COMN.
Therefore, a potential level of a negative CML signal CML_SIGb outputted through the negative output node OUT_NDb decreases, and a potential level of a positive CML signal CML_SIG outputted through the positive output node OUT_ND increases.
On the other hand, when a potential level of the positive input signal INPUT_SIG decreases and the first NMOS transistor N1 is turned off, a voltage level of the negative input signal INPUT_SIGb increases and the second NMOS transistor N2 is turned on. Accordingly, a current I1 does not flow from the negative output node OUT_NDb to the common node COMN, but a predetermined current I2 continuously flows from the positive output node OUT_ND to the common node COMN.
Therefore, a potential level of the negative CML signal CML_SIGb outputted through the negative output node OUT_NDb increases, and a potential level of the positive CML signal CML_SIG outputted through the positive output node OUT_ND decreases.
The decrease degree of the potential level of the CML signal (CML_SIG, CML_SIGb) may vary depending on the resistance of a first resistor R1 and the resistance of a second resistor R2. This is because the potential level of the CML signal (CML_SIG, CML_SIGb) decreases depending on how much the potential amount changes while the current I1 or I2 passes through the first resistor R1/the first NMOS transistor N1/the third NMOS transistor or the second resistor R2/the second NMOS transistor N2/the third NMOS transistor N3.
Thus, the potential level of the CML signal (CML_SIG, CML_SIGb) is determined depending on a voltage division formed by the current I1 between the first resistor R1, the first NMOS transistor N1, and the third NMOS transistor N3, or a voltage division formed by the current I2 between the second resistor R2, the second NMOS transistor N2, and the third NMOS transistor N3.
The first resistor R1 and the second resistor R2 have the same resistance. Therefore, as the resistance of the first resistor R1 and the second resistor R2 increases, the potential level of the CML signal (CML_SIG, CML_SIGb) approaches the level of the ground voltage VSS. As the resistance of the first resistor R1 and the second resistor R2 decreases, the potential level of the CML signal (CML_SIG, CML_SIGb) shifts far away from the level of the ground voltage VSS.
On the other, the increase degree of the potential level of the CML signal (CML_SIG, CML_SIGb) is determined in the state where a current does not continuously flow through the first resistor R1 and the second resistor R2. Therefore, the potential level of the CML signal (CML_SIG, CML_SIGb) increases up to the same level as the power supply voltage VDD.
FIG. 2 is a graph illustrating a change in the current amount depending on a change in the operation frequency, which is consumed by the circuit of FIG. 1 for generating or transferring a CML signal in a conventional integrated circuit.
Referring to FIG. 2, it can be seen that a circuit 100 for generating or transferring the CML signal (CML_SIG, CML_SIGb) in a conventional integrated circuit consumes a constant current regardless of a change in the operation frequency.
The input signals INPUT_SIG and INPUT_SIGb are classified into a positive input signal INPUT_SIG and a negative input signal INPUT_SIGb that have opposite phases. Therefore, the first NMOS transistor N1 and the second NMOS transistor N2, which operate in response to the input signals INPUT_SIG and INPUT_SIGb, are controlled such that when one of the first NMOS transistor N1 and the second NMOS transistor N2 is turned on, the other is turned off. That is, the first NMOS transistor N1 and the second NMOS transistor N2 are controlled such that they perform opposite operations.
The first NMOS transistor N1 and the second NMOS transistor N2 have the same size. Therefore, the total amount of the currents I1 and I2 flowing from the power supply voltage (VDD) terminal to the common node COMN does not change regardless of whether the potential levels of the input signals INPUT_SIG and INPUT_SIGb change, and regardless of whether the potential levels of the CML signals CML_SIG and CML_SIGb change.
The CML bias voltage CML_BIAS is a signal that always maintains a constant potential level. Therefore, while power is supplied to the integrated circuit, the third NMOS transistor N3 is always turned on to transfer a constant current I3 from the common node COMN to the ground voltage (VSS) terminal.
Thus, the circuit 100 for generating or transferring the CML signal (CML_SIG, CML_SIGb) consumes a constant current regardless of whether it is in a high frequency state where the potential levels of the input signals INPUT_SIG and INPUT_SIGb change at a high speed or in a low frequency state where the potential levels of the input signals INPUT_SIG and INPUT_SIGb change at a low speed.
However, that the circuit 100 consumes a constant current regardless of whether it is in a high frequency state or in a low frequency state may be advantageous when the circuit 100 is to operate at a high frequency, but may be disadvantageous when the circuit 100 is to operate at a low frequency.
That is, the circuit 100 consumes a relatively large current even when it can reduce a consumed current by operating at a low frequency. Therefore, the circuit 100 may consume an unnecessarily large current when it operates at a low frequency.
Therefore, the conventional circuit 100 of FIG. 1 may be modified as illustrated in FIG. 3.
Referring to FIG. 3, in comparison with the configuration of FIG. 1, a configuration is added that controls the resistance of the first resistor R1 and the resistance of the second resistor R2, which is used to determine the state of the decreasing potential levels of the CML signals CML_SIG and CML_SIGb, depending on a frequency setting code FRQ_CODE<0:3>.
Also, a configuration is added that controls the amount of the current I3, which flows from the common node COMN to the ground voltage (VSS) terminal in response to the CML bias voltage CML_BIAS, depending on the frequency setting code FRQ_CODE<0:3>.
By this configuration change, when the circuit 100 is to operate at a low frequency, the current consumption amount may be minimized by changing the value of the frequency setting code FRQ_CODE<0:3>.
However, in the circuit of detecting the optimal current amount depending on the operation frequency by changing the value of the frequency setting code FRQ_CODE<0:3> as illustrated in FIG. 3, because an operation of changing the resistance of the first resistor R1 and the resistance of the second resistor R2 and an operation of changing the amount of the current I3 flowing from the common node COMN to the ground voltage (VSS) terminal are simultaneously performed when the value of the frequency setting code FRQ_CODE<0:3> changes depending on a change in the operation frequency, the swing levels of the CML signals CML_SIG and CML_SIGb may fail to have a desired stable level.
At the circuit design stage, an operation of changing the resistance of the first resistor R1 and the resistance of the second resistor R2 depending on a change in the frequency setting code FRQ_CODE<0:3> and an operation of changing the amount of the current I3 flowing from the common node COMN to the ground voltage (VSS) terminal can be set to be performed complementarily. That is, a change in the swing levels of the CML signals CML_SIG and CML_SIGb due to an operation of changing the resistance of the first resistor R1 and the resistance of the second resistor R2 is compensated by an operation of changing the amount of the current I3 flowing from the common node COMN to the ground voltage (VSS) terminal, so that the swing levels of the CML signals CML_SIG and CML_SIGb can always have a desired level.
However, in the process of using the fabricated integrated circuit, due to a change in PVT (Process, Voltage, Temperature), an operation of changing the resistance of the first resistor R1 and the resistance of the second resistor R2 depending on a change in the frequency setting code FRQ_CODE<0:3> and an operation of changing the amount of the current I3 flowing from the common node COMN to the ground voltage (VSS) terminal may be performed without the compensation.
Thus, the swing levels of the CML signals CML_SIG and CML_SIGb may have different levels from the target swing levels.
Therefore, a duty distortion of a signal may occur in the internal circuits of the integrated circuit using such CML signals CML_SIG and CML_SIGb.